• RF Transceiver Analog Devices ADRV9026 based FMC
• Vita 57.1-2010 specification compliant
• FMC High Pin Connector (HPC)
• JESD024B/C interface up to 24.33 Gbps
• 4x Tx Lanes
• 4x Rx Lanes
• LA Bus LVDS and Singled-Ended
• Operates with VAdj = 2.5V to 1.5V
• Air and Conduction Cooled compatible
• Quad Transmitters (Tx)
• Quad Receivers (Rx)
• Ext_Lo Input/Ouput
• External Reference Clock Input
• RF Coverage: 75MHz to 6.0 GHz
• Tx Synthesis Bandwidth Max: 450MHz
• Rx Bandwidth Max: 200MHz
• Support Time Division Duplex (TDD)
• Support Frequency Time Division (FTD)
• Fully integrated independent fractional-N radio frequency synthesizers
• On-board VCXO : 100.000MHz, 122.880MHz, 125.000MHz, 153.600MHz or 156.250MHz
• Air Cooled and Conduction Cooled

The FMC-ZU3RF-B is a FMC for RF wireless communications applications based on the ADRV9026 component from Analog Device Inc (ADI).

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution.

The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.

The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range.

The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband.

Other auxiliary functions such as analog-to-digital converters (ADCs), digital- to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths.

A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips.

All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.

PanaTeQ offers the VPX3-ZU1B-SDR-DB development system based on the VPX3-ZU1B 3U OpenVPX Zynq Ultrascale+ and the FMC-ZU3RF-B-W1A-AS for typical Software Defined Radio application, in both air-cooled and conduction cooled version.

• RF Transceiver Analog Devices ADRV9029 based FMC
• Vita 57.1-2010 specification compliant
• FMC High Pin Connector (HPC)
• JESD024B/C interface up to 24.33 Gbps
• 4x Tx Lanes
• 4x Rx Lanes
• LA Bus LVDS and Singled-Ended
• Operates with VAdj = 2.5V to 1.5V
• Air and Conduction Cooled compatible
• Quad Transmitters (Tx)
• Quad Receivers (Rx)
• Ext_Lo Input/Ouput
• External Reference Clock Input
• RF Coverage: 75MHz to 6.0 GHz
• Tx Synthesis Bandwidth Max: 450MHz
• Rx Bandwidth Max: 200MHz
• Support Time Division Duplex (TDD)
• Support Frequency Time Division (FTD)
• Fully integrated independent fractional-N radio frequency synthesizers
• On-board VCXO : 100.000MHz, 122.880MHz, 125.000MHz, 153.600MHz or 156.250MHz
• Air Cooled and Conduction Cooled

The FMC-ZU3RF-A is a FMC for RF wireless communications applications based on the ADRV9029 component from Analog Device Inc (ADI).

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution.

The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.

The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range.

The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband.

Other auxiliary functions such as analog-to-digital converters (ADCs), digital- to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths.

A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips.

All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.

PanaTeQ offers the VPX3-ZU1B-SDR-D development system based on the VPX3-ZU1B 3U OpenVPX Zynq Ultrascale+ and the FMC-ZU3RF-A-W1A-AS for typical Software Defined Radio application, in both air-cooled and conduction cooled version.

• FMC+ Vita 57.4 specification compliant
• JESD024B/C interface up to 20/32.5 Gbps
• 24x TX Lanes
• 24x RX Lanes
• Operates with VAdj = 2.5V to 1.5V
• Air and Conduction Cooled compatible
• Quad ADC Channels (12-bit up to 20GSPS)
• Quad DAC Channels (16-bit up to 28GSPS)
• Uses of 10x 12GHz bandwidth SSMC connectors
• Inputs with Impedance of 50 ohms AC Coupled
• Analog Bandwidth Input Up to TBD GHz
• Reference Clock Input
• FPGA GPIO direct Input or Output
• On-board VCXO

The FMC-MXFE4-A is a FMC+ for High-Speed Data Acquisition applications based on the AD9084 Quad 12-bit ADC and Quad 16-bit DAC from Analog Devices Inc (ADI).

The AD9084 mixed signal front-end (MxFE®) is a highly integrated device with a 16-bit, 28 GSPS maximum sample rate, RF digital-to-analog converter (DAC) core, and 12-bit, 20 GSPS maximum sample rate, RF analog-to-digital converter (ADC) core. The AD9084 supports four transmit channels and four receive channels.

The AD9084 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) having wide instantaneous bandwidth.

The device features a 48 lane, 32.5 Gbps JESD204C or 20 Gbps JESD204B data transceiver port, an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband, direct to RF applications.

The AD9084 also features a bypass mode that allows the full bandwidth capability of the ADC and/or DAC cores to bypass the DSP datapaths.

The device also features low latency loopback and frequency hopping modes targeted at phased array radar systems and electronic warfare applications.

PanaTeQ offers the VPX3-VERSA2-MXFE4-A-CAA-AS development system based on the VPX3-VERSA2 3U VPX VERSAL and the FMC-MXFE4-A-AAA for typical Digital Signal Processing.

• VITA 57.1-2010 specification compliant
• Fully HW/SW compatible with ADRV9009 Evaluation Board
• FMC High Pin Connector (HPC)
• JESD024B interface up to 12288 Mbps
• LA Bus LVDS and Singled-Ended
• Operates with VAdj = 2.5V to 1.5V
• Air and Conduction Cooled compatible design
• 2x SSMC for Dual Transmitters (Tx)
• 2x SSMC for Dual Receivers (Rx)
• 2x SSMC for Dual Observation Receiver (ORx, 450MHz BW max)
• 1x SSMC RF Ext LO Input/Output
• 1x SSMC Reference Clock Input
• 2x SSMC Dual GPIO (3.3V) In and Out to/from FMC connector
• RF Coverage: 75MHz to 6.0 GHz
• Tx Synthesis Bandwidth Max: 450MHz
• Rx Bandwidth Max: 200MHz
• Support Time Division Duplex (TDD)
• Fully integrated independent fractional-N radio frequency synthesizers
• On-board VCXO : 100.000MHz, 122.880MHz, 125.000MHz, 153.600MHz or 156.250MHz

The FMC-ZU2RF-A is a FMC for RF wireless communications applications based on the ADRV9009 component from Analog Devices Inc (ADI).

The ADRV9009 component is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G/5G micro and macro base station equipment TDD applications.

The receiver path consists of two independent, wideband, direct conversion receivers with state-of-the-art dynamic range.

The part also support a wide-bandwidth time-shared observation path receiver for use in TDD applications. The complete receiver subsystem includes automatic and manual attenuation  control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need of these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-Front-End control are also integrated.

In addition to the autonomous AGC, it also has flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.

The received signals are digitized with a set of four high-dynamic range continuous-time sigma-delta ADCs which provide inherent anti-aliasing. The combinaison of the direct conversion architecture, which does not suffer from out-of-band mixing, and lack of aliasing relaxes the requirements of the RF filters compared as the traditional IF receivers.

The transmitters use an innovative direct conversion modulator that archives high modulation accuracy with exceptional low noise.

The observation path consists of a wide bandewidht direct conversion receiver with state-of-the-art dynamic range.

The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver paths. An additional synthetiser generates the clocks needed for the converters, digital circuits, and serial interface. All voltage-controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.

The high speed JESD204B interface supports up to 12 288 Mbps lane rates resulting in two lanes per transmitter, and a single lane per receiver in the widest bandwidth mode.

The interface also supports interleaved mode for lower bandwidths thus reducing the total of high-speed data interface lane to one.

PanaTeQ offers the VPX3-ZU1B-SDR-C development system based on the VPX3-ZU1B 3U OpenVPX Zynq Ultrascale+ and the FMC-ZU2RF-A-W1A-AS for typical Software Defined Radio application, in both air-cooled and conduction cooled version.

• Vita 57.1-2010 specification compliant
• FMC High Pin Connector (HPC)
• JESD024B interface up to 6144 Mbps
• LA Bus LVDS and Singled-Ended
• Operates with VAdj = 2.5V to 1.5V
• Air and Conduction Cooled compatible
• Fully ADRV9375 HW/SW compatible
• Dual Transmitters (Tx)
• Dual Receivers (Rx)
• Observation Receiver (ORx) with 2 inputs
• Fully integrated ultralow power DPD actuator and adaptation engine for PA linearization
• Sniffer Receiver (SnRx) with 1 input
• TX Ext LO Input/Output
• RX Ext LO Input/Output
• Reference Clock Input or Output
• FPGA GPIO direct Input or Output
• RF Coverage 300 MHz to 6.0 GHz
• Tx Synthesis Bandwidth (BW) to 250 MHz
• Rx Bandwidth: 7 MHz to 100 MHz
• Support Time Division Duplex (TDD)
• Support Frequency Division Duplex (FDD)
• Fully integrated independent fractional-N radio frequency synthesizers
• On-board VCXO : 100.000 MHz, 122.880 MHz, 153.600 MHz or 156.250 MHz

The FMC-ZU1RF-B is a FMC for RF wireless communications applications based on the AD9375 component from Analog Device Inc (ADI).

This FMC is fully hardware and software compatible with the ADRV9375 evaluation board from ADI.

The AD9375 component is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, a fully integrated digital predistorsion (DPD) actuator and adaptation engine, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro base station equipment in both FDD and TDD applications.

The AD9375 operates from 300 MHz to 6000 MHz, covering most of the licensed and unli-censed cellular bands. The DPD algorithm supports linearization on signal bandwidth up to 40 MHz depending on the power amplifier (PA) charecteristics.

The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.

The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correc-tion, quadrature error correction, and programmable digital filters, eliminating the need for these functions in the digital baseband.

Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.

An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.

The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.

The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver, the observation receiver, and the clock sections. Careful design and layout techniques provide the isolation demanded in high perfor-mance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.

• Vita 57.1-2010 specification compliant
• FMC High Pin Connector (HPC)
• JESD024B interface up to 6144 Mbps
• LA Bus LVDS and Singled-Ended
• Operates with VAdj = 2.5V to 1.5V
• Air and Conduction Cooled compatible
• Fully ADRV9371 HW/SW compatible
• Dual Transmitters (Tx)
• Dual Receivers (Rx)
• Observation Receiver (ORx) with 2 inputs
• Sniffer Receiver (SnRx) with 1 input
• TX Ext LO Input/Output
• RX Ext LO Input/Output
• Reference Clock Input or Output
• FPGA GPIO direct Input or Output
• RF Coverage 300MHz to 6.0 GHz
• Tx Synthesis Bandwidth (BW) to 250MHz
• Rx Bandwidth: 7MHz to 100MHz
• Support Time Division Duplex (TDD)
• Support Frequency Division Duplex (FDD)
• Fully integrated independent fractional-N radio frequency synthesizers
• On-board VCXO : 100.000MHz, 122.880MHz, 153.600MHz or 156.250MHz

The FMC-ZU1RF-A is a FMC for RF wireless communications applications based on the AD9371 component from Analog Devices Inc (ADI).

This FMC is fully hardware and software compatible with the ADRV9371 evaluation board from ADI.

The AD9371 component is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro base station equipment in both FDD and TDD applications.

The AD9371 operates from 300 MHz to 6000 MHz, covering most of the licensed and unli-censed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.

The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correc-tion, quadrature error correction, and programmable digital filters, eliminating the need for these functions in the digital baseband.

Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.

An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.

The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.

The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver, the observation receiver, and the clock sections. Careful design and layout techniques provide the isolation demanded in high perfor-mance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.

PanaTeQ offers the VPX3-ZU1B-SDR-A development system based on the VPX3-ZU1B 3U OpenVPX Zynq Ultrascale+ and the FMC-ZU1RF-A for typical Software Defined Radio application.