3U VPX SDR Module
AMD Zynq UltraScale+ MPSoC
Analog Devices AD9371

specifications
- 3U OpenVPX module, Air-Cooled
- AMD Zynq Ultrascale+ MPSoC ZU6/ZU9/ZU15 FFVC900E package
- Up to 8GB PS DDR4-2400 memory 64-bit, 8-bit ECC
- Up to 2GB PL DDR4-2400 memory 16-bit, no ECC
- Up to 256GB eMMC managed NAND Flash
- FMC HPC site with 10x MGTs @ up to 16.3Gb/s
- AD9371 Wideband RF Transceiver
- Dual Transmitter (Tx), Dual Receiver (Rx)
- Observation Receiver (ORx) with 2 inputs
- Sniffer Receiver (SnRx) with 1 input
- Reference Clock Input
- RF Coverage 300MHz to 6.0 GHz
- Tx Synthesis Bandwidth (BW) to 250MHz
- Rx Bandwidth: Up to 100MHz
- On-Board VCXO @ 122.88MHz.
Typical Applications
- Software Defined Radio
- Wireless Infrastructure 3G/4G
- FDD and TDD active Antenna Systems
- Electronic Warfare
- Drones and UAVs
- Military Communications
Description
PanaTeQ’s VPX3-ZU1B-SDR-A is a 3U OpenVPX modules based on the Zynq UltraScale+ MPSoC device from AMD coupled to RadioVerse Analog Devices RF Wideband Transceiver AD9371 for a broad range of applications such as Software Defined Radio, MILCOM, massive MIMO, Phase Array Radar and Electronic Warfare.
PanaTeQ provides solutions for Ruggedized Air-Cooled and Conduction Cooled systems.
These VPX3-ZU1B-SDR-A module is based on the following PanaTeQ’s sub-modules (boards):
The VPX3-ZU1B is a 3U OpenVPX module based on a AMD Zynq Ultrascale+ MPSoC with a FMC 57.1 site, HW/SW compatible with ZCU102 Evaluation board from AMD.
The FMC-ZU1RF-A is a FMC based on an Analog Devices AD9371, HW/SW compatible with ADRV9371 Evaluation Board from Analog Devices.

Document / link list
FMC Mezzanine
Wideband RF Transceiver
Analog Devices AD9371

specifications
- Vita 57.1-2010 specification compliant
- FMC High Pin Connector (HPC)
- JESD024B interface up to 6144 Mbps
- LA Bus LVDS and Singled-Ended
- Operates with VAdj = 2.5V to 1.5V
- Air and Conduction Cooled compatible
- Fully ADRV9371 HW/SW compatible
- Dual Transmitters (Tx)
- Dual Receivers (Rx)
- Observation Receiver (ORx) with 2 inputs
- Sniffer Receiver (SnRx) with 1 input
- TX Ext LO Input/Output
- RX Ext LO Input/Output
- Reference Clock Input or Output
- FPGA GPIO direct Input or Output
- RF Coverage 300MHz to 6.0 GHz
- Tx Synthesis Bandwidth (BW) to 250MHz
- Rx Bandwidth: 7MHz to 100MHz
- Support Time Division Duplex (TDD)
- Support Frequency Division Duplex (FDD)
- Fully integrated independent fractional-N radio frequency synthesizers
- On-board VCXO : 100.000MHz, 122.880MHz, 153.600MHz or 156.250MHz
Typical Applications
- Software Defined Radio
- Wireless Infrastructure 3G/4G
- FDD and TDD active Antenna Systems
- Electronic Warfare
- Drones and UAVs
- Military Communications
Description
The FMC-ZU1RF-A is a FMC for RF wireless communications applications based on the AD9371 component from Analog Devices Inc (ADI).
This FMC is fully hardware and software compatible with the ADRV9371 evaluation board from ADI.
The AD9371 component is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro base station equipment in both FDD and TDD applications.
The AD9371 operates from 300 MHz to 6000 MHz, covering most of the licensed and unli-censed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.
The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correc-tion, quadrature error correction, and programmable digital filters, eliminating the need for these functions in the digital baseband.
Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.
An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.
The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.
The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver, the observation receiver, and the clock sections. Careful design and layout techniques provide the isolation demanded in high perfor-mance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.
PanaTeQ offers the VPX3-ZU1B-SDR-A development system based on the VPX3-ZU1B 3U OpenVPX Zynq Ultrascale+ and the FMC-ZU1RF-A for typical Software Defined Radio application.
