FMC-ZU2RF-A

• VITA 57.1-2010 specification compliant
• Fully HW/SW compatible with ADRV9009 Evaluation Board
• FMC High Pin Connector (HPC)
• JESD024B interface up to 12288 Mbps
• LA Bus LVDS and Singled-Ended
• Operates with VAdj = 2.5V to 1.5V
• Air and Conduction Cooled compatible design
• 2x SSMC for Dual Transmitters (Tx)
• 2x SSMC for Dual Receivers (Rx)
• 2x SSMC for Dual Observation Receiver (ORx, 450MHz BW max)
• 1x SSMC RF Ext LO Input/Output
• 1x SSMC Reference Clock Input
• 2x SSMC Dual GPIO (3.3V) In and Out to/from FMC connector
• RF Coverage: 75MHz to 6.0 GHz
• Tx Synthesis Bandwidth Max: 450MHz
• Rx Bandwidth Max: 200MHz
• Support Time Division Duplex (TDD)
• Fully integrated independent fractional-N radio frequency synthesizers
• On-board VCXO : 100.000MHz, 122.880MHz, 125.000MHz, 153.600MHz or 156.250MHz

The FMC-ZU2RF-A is a FMC for RF wireless communications applications based on the ADRV9009 component from Analog Devices Inc (ADI).

The ADRV9009 component is a highly integrated, wideband RF transceiver offering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G/5G micro and macro base station equipment TDD applications.

The receiver path consists of two independent, wideband, direct conversion receivers with state-of-the-art dynamic range.

The part also support a wide-bandwidth time-shared observation path receiver for use in TDD applications. The complete receiver subsystem includes automatic and manual attenuation  control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need of these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-Front-End control are also integrated.

In addition to the autonomous AGC, it also has flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.

The received signals are digitized with a set of four high-dynamic range continuous-time sigma-delta ADCs which provide inherent anti-aliasing. The combinaison of the direct conversion architecture, which does not suffer from out-of-band mixing, and lack of aliasing relaxes the requirements of the RF filters compared as the traditional IF receivers.

The transmitters use an innovative direct conversion modulator that archives high modulation accuracy with exceptional low noise.

The observation path consists of a wide bandewidht direct conversion receiver with state-of-the-art dynamic range.

The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis for the transmitter, the receiver paths. An additional synthetiser generates the clocks needed for the converters, digital circuits, and serial interface. All voltage-controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.

The high speed JESD204B interface supports up to 12 288 Mbps lane rates resulting in two lanes per transmitter, and a single lane per receiver in the widest bandwidth mode.

The interface also supports interleaved mode for lower bandwidths thus reducing the total of high-speed data interface lane to one.

PanaTeQ offers the VPX3-ZU1B-SDR-C development system based on the VPX3-ZU1B 3U OpenVPX Zynq Ultrascale+ and the FMC-ZU2RF-A-W1A-AS for typical Software Defined Radio application, in both air-cooled and conduction cooled version.